Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink

Hardware-in-the-loop testing is usually a part of the design cycle control systems. Efficient and fast models can be created in Hardware Description Language (HDL), which implemented Field-Programmable Gate Array (FPGA). Control engineers are more skilled higher-level approaches. HDL derived automatically from schematics have noticeably lower performance, while their equations faster smaller. However, even translated into using might worse than manually coded models. A workflow proposed to achieve manual-like performance with automatic tools. It consists identification similar operations, forcing signal signedness, adjusting multiplier input sizes. detailed comparison was performed between three workflows: (1) translation high-level MATLAB code, (2) Simulink model, (3) working directly HDL. Sources inefficiency were shown buck converter, process validated full-bridge electrical losses Runge–Kutta method. The results showed that approach delivered code very close reference VHDL implementation, for complex designs. Finally, model an off-the-shelf FPGA board suitable hardware-in-the-loop test setup.